The present invention relates to a semiconductor device and a wireless communication device, in particular, to a semiconductor device and a wireless communication device including a power-on reset circuit.
A power-on reset circuit is used to prevent an internal state of a logic circuit from being indeterminate when the power is turned on. The power-on reset circuit detects a rise of the power and supplies a reset signal RESET or an inverted signal thereof RESETB to the logic circuit. As an example of the power-on reset circuit, FIG. 1 shows a conceptual diagram of a circuit described in Japanese Patent Laid-Open No. 1991-48519 (See Patent Document 1).
As shown in FIG. 1, the power-on reset circuit described in Patent Document 1 includes two diode circuits 901 and 902 formed between a VDD terminal 101 and a GND terminal 102 and a comparator CM100 for detecting a voltage difference between voltage detection nodes 911 and 912 of the diode circuits 901 and 902. The diode circuit 901 includes a resistor R100 and a pn junction diode D100 which are connected in series between the VDD terminal 101 and the GND terminal 102. The cathode of the diode D100 is coupled to the GND terminal 102 and the anode thereof is coupled to the VDD terminal 101 through the resistor R100 to be the voltage detection node 911. The diode circuit 902 includes resistors R200 and R300 and a pn junction diode D200 which are connected in series between the VDD terminal 101 and the GND terminal 102. The cathode of the diode D200 is coupled to the GND terminal 102 and the anode thereof is coupled to the VDD terminal 101 through the resistors R300 and R200. The coupling node between the resistors R200 and R300 is the second voltage detection node 912. The comparator CM100 outputs a comparison result between an output voltage V 10 outputted from the voltage detection node 911 and an output voltage V20 outputted from the voltage detection node 912 as a reset signal RESETB.
An example of a setting method of parameters of each element in the power-on detection circuit shown in FIG. 1 will be described. Here, the resistances of the resistors R100, R200, and R300 are defined as “R100”, “R200”, and “R300” respectively. As a typical setting example of each element parameter, there is a method in which the resistances of resistors R100 and R200 are set to be the same (“R100=R200”), the size ratio between the diodes D100 and D200 is set to be 1:N, and an appropriate value of “R300” is set. Alternatively, there is a setting method in which a ratio between a product of the size of the diode D100 and the value “R200” of the resistor R200 and a product of the size of the diode D200 and the value “R100” of the resistor R100 is set to be 1:N and the value “R300” of the resistor R300 is set appropriately.
FIG. 2A shows response characteristics of the output voltages V1 and V2 with respect to the power supply voltage VDD in the circuit shown in FIG. 1. As shown in FIG. 2A, when the power supply voltage VDD rises from zero, an external voltage (here, the power supply voltage VDD) almost directly becomes the output voltages V10 and V2 (from time T0 to time T10) because no current flows through the diodes D100 and D200 at a voltage lower than or equal to the forward drop voltage “VF” of the diodes. Further, when the voltage becomes higher than “VA”, the current through the diode D200 with a larger size becomes non-negligible and the increase of the output voltage V20 becomes gradual. When the voltage is raised further, the current through the diode D100 with a smaller size also becomes non-negligible and the increase of the output voltage V10 also becomes gradual. When the voltage is raised further, while the output voltage V10 rises by an increase of the voltage across terminals of the diode D100, the output voltage V20 rises by an increase of the sum of the voltage across terminals of the diode D200 and the voltage across terminals of the resistor R300. Therefore, the rate of the increase of the output voltage V20 is higher than that for the output voltage V10. The magnitude correlation of the output voltages V10 and V20 changes at the point where the power supply voltage becomes the voltage VB (time T20).
Here, FIG. 2B shows response characteristics of the comparator CM100 with respect to the power supply voltage VDD. As shown in FIGS. 2A and 2B, since the magnitude correlation of the output voltages V10 and V20 is indeterminate from the time T0 to the time T10, the value (signal level) of the output (reset signal RESETB) of the comparator CM100 may become indeterminate. However, it is not matter in practice since the reset signal RESETB with an appropriate signal level (low level) for the power-on reset operation is outputted after the time T10. Since the rate of increase in the output voltage V20 decreases earlier than that for the output voltage V10, “V10>V20” is established at the time T10, and the reset signal RESETB indicates a low level “VL (GND level)”. When the power supply voltage VDD rises further and exceeds a predetermined voltage “VB” at the time T20, the output voltage V20 with a higher rise rate exceeds the output voltage V10 and “V10 <V20” is established. Thereby, the reset signal RESETB changes to an expected value that indicates a high level. In a period of time from T20 to the time T30 at which the power supply voltage VDD becomes a predetermined voltage VC (an expected value of the power supply voltage VDD), the reset signal RESETB rises with “VH (VDD level)”. When the power supply voltage VDD becomes stable at the voltage VC, the reset signal RESETB also becomes stable at the “VH (VDD level)”.
It is known that if the size ratio between the diode D100 and the diode D200 and the value of the resistor R300 are appropriately selected, the voltage VB when “V10=V20” is established becomes a band gap voltage VBG of silicon and the effects of variations of temperature and elements can be reduced. In other words, the present circuit has an advantage to be tolerant to element variation and temperature variation. It is possible to adjust the voltage VB while controlling the effects of variations of temperature and elements within an allowable range by further appropriately changing circuit parameters from the state described above. In summary, the present circuit satisfies requirements for the power-on reset circuit.
A semiconductor device that can stably detect power-on regardless of parameters of voltage rising and a voltage level of an external power supply voltage is described in Japanese Patent Laid-Open No. 2005-109659 (See Patent Document 2). The semiconductor device described in Patent Document 2 delays a power-on signal with respect to a rapidly rising external power supply voltage by connecting a capacitance element to each of the diodes D100 and D200 shown in FIG. 1 in parallel.